1. Field of the Invention
The present invention relates to a method of producing a semiconductor device using sidewall spacers to obtain alignment of overlying device features. The present invention in particular relates to a method of producing a field-effect transistor using sidewall spacers on a semiconductor substrate for adjusting the position of an active region with respect to a gate electrode without realigning steps during the production process.
2. Description of the Related Art
The manufacturing process of integrated circuits involves the fabrication of numerous insulated gate field-effect transistors, such as metal-oxide semiconductor field-effect transistors (MOSFETs). In order to increase integration density and improve device performance, for instance, with respect to signal processing time and power consumption, feature sizes of the transistor structures are steadily decreasing. Most importantly, not only the gate length but also the length of the active region of the fabricated transistors needs to be reduced to comply with these requirements in order to reduce parasitic source and drain capacitances.
Conventionally, device features are defined and delineated by lithographic techniques, in particular photolithography, preferably using a high numerical aperture lens and a deep ultraviolet (DUV) light source. Current DUV lithography reaches its resolution limit at a feature size of approximately 0.2 xcexcm. Together with emerging gate length trim techniques, it is possible to reach device features in the sub-100 nm region. Such feature definition by lithography requires a plurality of process steps, each usually involving a resist mask technique. Overlay alignment of subsequent resist masks using special alignment features on the semiconductor substrate requires exact positioning of a mechanical stage supporting the substrate. Desirably, the overlay accuracy is considerably higher than the smallest feature size, preferably, at least one order of magnitude.
However, mechanical alignment of the various resist mask layers necessary for production of a field-effect transistor (FET) structure having a gate length of approximately 0.1 xcexcm is very difficult to achieve due to the mechanical nature of the overlay alignment process.
To comply with the general requirements of mass production of semiconductor devices, any new technology must conserve the current standards of efficiency, reliability, and cost of already existing methods or provide improvements in this respect.
As mentioned above, the formation of the active region relative to the gate electrode is a critical step in the manufacturing process of a field-effect transistor. The gate length dimension, i.e., the lateral extension of the gate electrode between the source region and drain region of the field-effect transistor, is commonly known as critical dimension of the gate. This critical dimension is desirably reduced to sizes approaching or even exceeding the resolution limit of the optical imaging systems used for patterning the device features. In a field-effect transistor such as a MOSFET, the gate is used to control an underlying channel formed in the semiconductor substrate between source region and drain region. Channel, source region, and drain region are formed in, on, or over a semiconductor substrate which is doped inversely to the drain and source regions. The gate electrode is separated from the channel, the source region, and the drain region, by a thin insulating layer, generally by an oxide layer. Additionally, device insulation features are necessary to ensure electrical isolation between neighboring field-effect transistors in integrated circuits.
During operation of such a MOSFET, a voltage is supplied to the gate electrode in order to create an electric field between the gate electrode and the source and drain regions affecting conductivity in the channel region of the substrate. Besides the desired transistor current control function, the gate electrode, the gate insulation layer, and the regions underlying the gate insulation layer, also act as a capacitor generating a parasitic capacitance. The amount of this parasitic capacitance depends on the feature size of the gate electrode. Most commonly in integrated circuit applications, the transistors are operated in a switching mode with clock frequencies currently as high as 400 to 500 MHz. In this operation mode, the gate capacitor has to be continuously charged and discharged, which significantly affects signal performance and power consumption of the device.
Moreover, the electric field between the source region and the drain region generates an additional parasitic capacitance. The amount of this additional parasitic capacitance depends on the sizes of the source region and of the drain region. This additional parasitic capacitance also significantly affects signal performance and power consumption of the semiconductor device. Decreasing sizes of the source region and of the drain region will reduce the additional parasitic capacitance. Decreasing source and drain regions, however, require difficult aligning steps during the photolithography for patterning the gate electrode, and, thus, lead to a deterioration of device characteristics due to an unavoidable misalignment of the gate electrode with respect to the source and drain regions because of the mechanical nature of the alignment step.
Due to the limitations of standard photolithography including mechanical alignment used to pattern and position the gate electrode within the active transistor region in which the drain and source have to be formed, advanced techniques for trimming the gate electrode will neither be translated into a decreasing size of the active region and, thus, into reduced source and drain regions, nor into reduced source and drain capacitances nor into an increased circuit-density.
As the dimensions of the transistor significantly influence its electrical characteristics, when decreasing device dimensions it is important to provide a method of reliably and reproducibly forming and positioning device features and device insulation features in order to minimize variations in the electrical characteristics of integrated circuits.
With reference to FIGS. 1a-1c, an illustrative example of forming a field-effect transistor according to a typical prior art process will be described. It is to be noted that FIGS. 1a-1c, as well as the following drawings in this application, are merely schematic depictions of the various stages in manufacturing the illustrative device under consideration. The skilled person will readily appreciate that the dimensions shown in the figures are not true to scale and that different portions or layers are not separated by sharp boundaries as portrayed in the drawings but may instead comprise continuous transitions. Furthermore, various process steps as described below may be performed differently depending on particular design requirements. Moreover, in this description, only the relevant steps and portions of the device necessary for the understanding of the present invention are considered.
FIG. 1a shows a schematic cross-section of a field-effect transistor at a specific stage of a typical prior art manufacturing process. Within a silicon substrate 1, shallow trenches 2, e.g., made of silicon dioxide, are formed and define a transistor active region 3 in which a channel, a drain region and a source region will be formed. A gate insulation layer 4 is formed above the substrate 1. The gate insulation layer 4 may be formed by a variety of techniques, e.g., thermal growth, chemical vapor deposition (CVD), etc., and it may be comprised of a variety of materials, e.g., an oxide, an oxynitride, silicon dioxide, etc.
FIG. 1b shows a schematic cross-section of the field-effect transistor of FIG. 1a after formation of a layer of gate electrode material 5 above the gate insulation layer 4. The layer of gate electrode material 5 may be formed from a variety of materials, e.g., polysilicon, a metal, etc., and it may be formed by a variety of techniques, e.g., CVD, low pressure chemical vapor deposition (LPCVD), sputter deposition, etc. Over the layer of gate electrode material 5, a resist feature 6 is formed. The process steps involved in patterning a layer of resist (not shown) for producing the resist feature 6 are of common knowledge to the skilled person. These steps include the formation of the layer of resist by a spin-coating process, and the employment of short exposure wavelengths, such as wavelengths in the DUV range, while performing the required photolithography steps. Since these procedures are commonly known, the description thereof will be omitted.
FIG. 1c shows a schematic cross-section of the field-effect transistor of FIG. 1b after conventional etching of the layer of gate electrode material 5 and after removing all remaining parts of resist feature 6. As a result of these process steps, a gate electrode 7 is obtained. Lightly doped drain (LDD) regions 10 are then formed in the active region 3 by a shallow ion implantation with a low dose before the formation of sidewall spacers 8. Next, the sidewall spacers 8 are formed adjacent the gate electrode 7. Thereafter, source and drain regions 9 are formed by a deep ion implantation with a high dose. The implanted ions are electrically activated by rapid thermal annealing (RTA). In order to form the sidewall spacers 8 adjacent to the gate electrode 7, silicon dioxide (SiO2) was blanket deposited and subsequently anisotropically etched. According to the conventional fabrication process as described above, drain and source regions 9 are limited by lightly doped drain and source regions 10, which connect to a channel 11. The transverse dimension of the gate electrode 7 defines a critical dimension 12, and the transverse dimension of the active region 3 defines a length dimension 13.
Since the source and drain regions 9 are defined by overlay alignment, i.e., mechanical alignment, in the various lithographic steps while forming the gate electrode, it is extremely difficult to decrease the length dimension 13 due to the mechanical nature of the alignment procedure. Therefore, advanced techniques for a desired down-sizing of the gate electrode 7 will not necessarily allow a corresponding scaling of the drain and source regions, and, thus, may not be translated into an increased circuit density or into reduced source and drain capacitances.
In view of the above-mentioned problems, a need exists for an improved method for forming the source region, the drain region, and the gate electrode of field-effect transistors on semiconductor substrates and to precisely align the gate electrode within the active region.
The present invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a gate electrode and sidewall spacer masking procedure both for forming the device isolation features and the source and drain regions.
According to a first embodiment of the invention there is provided a method of forming a field-effect transistor in an integrated circuit comprising the steps of providing a semiconductor substrate having a surface, forming a gate electrode over the surface, the gate electrode having a gate width and sidewalls along its width direction, forming first sidewall spacers having a first lateral extension along the sidewalls of the gate electrode, removing portions of the semiconductor substrate adjacent the first sidewall spacers, using the first sidewall spacers as a masking material for defining trenches and an active region, and forming device insulation features at the trenches.
According to a second embodiment of the invention there is provided a method of forming a field-effect transistor in an integrated circuit comprising the steps of providing a semiconductor substrate having a surface, forming a thin insulating layer over the surface, forming a gate electrode over the thin insulating layer, the gate electrode having a gate length direction and sidewalls along a gate width direction, forming a gate cover layer over the gate electrode and first sidewall spacers along the sidewalls of the gate electrode, the first sidewall spacers having a first lateral extension, masking and etching the gate cover layer and the first sidewall spacers so as to remove the first sidewall spacers along the gate length direction while maintaining the first sidewall spacers along the gate width direction, removing material of the semiconductor substrate adjacent the first sidewall spacers and the gate electrode, using the first sidewall spacers and the gate cover layer as a masking material for defining trenches and an active region, growing a thin thermal oxide film in the trenches for the benefit of trench corner rounding, filling the trenches with insulating material, polishing the insulating material back until the gate cover layer is exposed, etching the insulating material isotropically back, removing the gate cover layer and the first sidewall spacers, forming second sidewall spacers along the sidewalls of the gate electrode, the second sidewall spacers having a second lateral extension which is less than the first lateral extension, and forming source and drain regions in the active region.
The present invention as outlined above enables one to fabricate a transistor device having reduced device dimensions, wherein the active region, as well as device insulation features, are aligned with respect to the gate electrode without any overlay steps. With the production method provided by this invention, the active region of a field-effect transistor may be tuned to minimum desired dimensions regardless of lithographic restrictions. Consequently, a drastically increasing circuit density and decreasing parasitic capacitances can be reached.
This invention will enable a significant reduction of field-effect transistor dimensions in integrated circuits and, therefore, a significant cost reduction in manufacturing in semiconductor industries can be achieved.